Flint Center, Cupertino, CA, Sunday-Tuesday, August 10-12, 2014.
[accordion] [tabs] [tab title=”Tutorials”]Tutorials
| Sun 8/10 | Tutorial | Title | Presenter | Affiliation |
| 8:00 AM | Breakfast | |||
| 9:00 AM | Emerging Trends in HW Support for Security | Welcome and Introduction | John Davis | |
| 9:05 AM | Security Basics | Ruby Lee | Princeton | |
| [spoiler title=”Abstract:“] I will give a very quick introduction to basic concepts in security. This includes defining what security is, what threat models are, steps in designing a secure hardware system, what security policies are, why access control is important, and what applying cryptography can and cannot do. This will give the newcomer to security an idea of how designing for security is different from designing for performance or power, and will be a quick refresher of important points for more experienced security designers. This material is important to frame our thinking of security designs, and to better understand the following presentations. Biography: Ruby B. Lee is the Forrest G. Hamrick Professor of Electrical Engineering at Princeton University. Her current research is in security-aware computer architecture, secure caches that do not leak information, secure cloud computing, secure virtual machines, smartphone security, running unvetted applications on sensitive data, and security verification. She has also done extensive past work on cryptography acceleration, very fast and novel bit permutation instructions, secure processors and hardware trust anchors. Prior to Princeton, Lee served as chief architect at Hewlett-Packard for processor architecture, multimedia architecture, and then security architecture. She was a founding architect of HP?s PA-RISC architecture and instrumental in the initial design of several generations of PA-RISC processors for HP?s business and technical computers. She helped in the widespread adoption of multimedia in commodity products by pioneering multimedia support in microprocessors and introducing the first real-time software video in low-end products. She was co-leader of the Intel-HP multimedia architecture team for 64-bit microprocessors. She created the first security roadmap for enterprise and e-commerce security for HP. Lee is an ACM Fellow and IEEE Fellow, and holds over 120 U.S. and international patents. Known as a foremost hardware security expert, Lee is often asked to serve on national committees for improving cyber security research, such as being co-leader of the U.S. National Cyber Leap Year Summit and co-authoring the National Academies? study mandated by Congress for improving cyber security research.[/spoiler] |
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| 9:50 AM | Mobile HW Security | Vikas Chandra | ARM | |
| [spoiler title=”Abstract:“] Mobile hardware security differs from other computer security in both the ubiquity of mobile devices and the wide range of sophistication of the user community. Mobile solutions need to be physically robust against a range of attacks and also able to interact with a large software community through simple and secure interfaces. This talk describes both the problem and solution space for mobile hardware security, with particular focus on the trusted execution environment approach that allows the secure and non-secure worlds to coexist on the same hardware. Biography: Vikas Chandra is a Principal Engineer in the Corporate R&D group at ARM. He received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University in 2004. Dr. Chandra is an author on 45+ publications and inventor on 15+ approved/pending patents. He serves as an Associate Editor for TCAS-I and is on the technical program committee for Symposium on VLSI Circuits, CICC, ISLPED, ITC and IRPS. Currently he also holds a Visiting Scholar position at Stanford University in the EE department. His research interests are in reliability aware design, hardware security, low-power custom circuit design, memory architecture and DFM. Dr. Chandra received the ACM-SIGDA Technical Leadership Award in 2009 and is a senior member of IEEE.[/spoiler] |
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| 10:35 AM | Secure Systems Design | Leendert Van Doorn | AMD | |
| [spoiler title=”Abstract: “]I will discuss the two basic tenants of secure systems design: Integrity and Isolation. Integrity, the mechanism by which you can ensure that a system exhibits the intended behavior and Isolation, the mechanism by which you can contain and restrict what a system can do or what can be done to it. I will illustrate both concepts with practical examples of secure boot, authenticated boot, secure hypervisors and physical secure coprocessors as well as the ecosystem elements such as key distribution services and a discussion of integrity challenges in modern SOC designs to make it all work together. The objective of this lecture is to give the student a broad overview of secure systems design elements and how they fit together in practice. The lecture notes contain references for further study. Biography: Dr. Leendert van Doorn is a Corporate Fellow and Corporate VP at AMD where he is responsible for driving software innovation across the company. He actively engages with AMD?s software partners to understand their long-term roadmaps and reflects this input back into AMD?s roadmaps, while at the same time evangelizing AMD?s future plans with AMD?s partners. Leendert is responsible for AMD?s security, virtualization, manageability, and software ecosystem strategies. During the last 4 years he has been actively driving AMD’s ARM 64-bit server ecosystem enablement. He is a member of AMD?s Innovation Leadership Team and actively participates in AMD?s domain roadmap process. Before joining AMD he was a Sr. Manager at IBM?s T.J. Watson Research Center where he lead virtualization, system security, penetration and security usability research teams. Leendert holds a Ph.D. from the Vrije Universiteit in Amsterdam, The Netherlands. Occasionally he is known to find refuge at Carnegie Mellon University where he is an adjunct professor.[/spoiler] |
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| 11:20 AM | Break | |||
| 11:35 AM | Mitigating Exploits, Rootkits and Advanced Persistent Threats | David Durham | Intel | |
| [spoiler title=”Abstract:“] I will cover new processor features that enable improved introspection and protection services to be applied within Operating Systems and applications for better defense against malware. This tutorial will uncover new instructions, exceptions and their usages to provide better end-point security solutions. New hardware breaks through performance barriers while enabling efficient co-existence between security solutions and platform virtualization solutions. I will also look forward to possible instruction set extensions that provide scalable trusted execution environments and reduce the attack surface for application software. Biography: David Durham is a Senior Principal Engineer and Director in Intel Labs. His research team developed anti-malware and cryptographic security features currently found in hundreds of millions of Intel processors. David also developed policy-based network management technologies, created security solutions shipping in Intel® vProTM platforms and worked with McAfee to deliver processor-based anti-malware products. Collaborating with industry leaders, his team developed IEEE 802.1 security protocols and advanced network access control capabilities now embedded in tens of millions of Intel platforms. He is a prolific author on computer communications, having written a book, multiple publications and several Internet protocol standards deployed in millions of connected devices. David received two Intel Achievement Awards, was granted over 100 US and international patents and earned his B.S. and M.S. degrees in Computer Engineering from Rensselaer Polytechnic Institute.[/spoiler] |
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| 12:20 AM | University Research in Hardware Security | Ruby Lee | Princeton | |
| [spoiler title=”Abstract:“] After presentations of industry security topics and designs by ARM, AMD and Intel, I will quickly survey key areas in hardware security research that have been done in universities. I give one example each of the two main categories of hardware security research: hardware-enhanced security versus secure hardware design. The focus is on hardware security technologies that are more mature and deployable, for the HotChips audience.[/spoiler] | ||||
| 12:50 PM | Q&A / Wrap-up | All speakers | ||
| 1:00 PM | Lunch | |||
| 2:00 PM | Internet of Things | Welcome | Behnam Robatmili | |
| 2:10 PM | Powering the Internet of Things | Yogesh Ramadass | TI | |
| [spoiler title=”Abstract:“] With the advent of IoT technology, a wide variety of electronic devices is expected to be deployed in often inaccessible places. Keeping these space-constrained devices powered up for their intended lifetimes is one of the primary concerns in the widespread adoption of this technology. In this tutorial, I will look at the energy needs of IoT devices, discuss the power delivery architecture and examine self-powered operation. The tutorial will delve into the basics of energy harvesting sources, storage mechanisms (batteries, supercapacitors) and the associated power management circuits needed(low-power DC/DC converters, chargers) to extend the operational lifetime of IoT devices. Biography: Yogesh Ramadass received his B. Tech. degree from the Indian Institute of Technology, Kharagpur in 2004 and the S. M. and Ph.D. degrees in Electrical Engineering from MIT in 2006 and 2009. He is currently working as a lead circuit design engineer at Texas Instruments where he is involved in the design of high voltage drivers and modules using Gallium Nitride FETs, next generation energy harvesting chips and low-power DC/DC converters. Dr. Ramadass was awarded the President of India Gold Medal in 2004 and the EETimes ?Innovator of the Year? award in 2013. He was a co-recipient of the Jack Kilby best student paper award at ISSCC 2009 and the Beatrice Winner award for editorial excellence at ISSCC 2007. He serves on the Technical Program Committee for ISSCC and ISLPED and as an associate editor for the IEEE Journal of Solid-State Circuits.[/spoiler] |
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| 3:00 | Ultra Low Power Design Approaches for IoT | Massimo Alioto | National University of Singapore | |
| [spoiler title=”Abstract:“] The continuous demand for smaller integrated systems with enhanced computation-ability has led to the Internet-of-Things as a viable concept in real-world applications. Aggressive reduction of the power consumption is a crucial aspect of integrated circuits for IoT, whose voltages typically need to be pushed down to near-threshold (and sometimes even below). This talk addresses the fundamental issues entailed by the operation at near-threshold and below and related solutions. Due to the significantly different performance/energy/resiliency/leakage design tradeoff at ultra-low voltages, this talk provides a fresh view on near-threshold circuits (and below) and debunks several wrong assumptions stemming from traditional low-power common wisdom. To put things in perspective, design trends at near-threshold and below are discussed, including fine-grain voltage distribution/power gating, heterogeneity, specialization, and the strong need for across-boundary design, among the others. Biography: Massimo Alioto (M?01?SM?07) was born in Brescia, Italy, in 1972. He received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. He is an Associate Professor at the Department of Electrical and Computer Engineering, National University of Singapore. Previously, he was Associate Professor at the Department of Information Engineering of the University of Siena. In 2013 he was also Visiting Scientist at Intel Labs ? CRL (Oregon) to work on ultra-scalable microarchitectures. In 2011-2012, he was Visiting Professor at University of Michigan, Ann Arbor, investigating on active techniques for resiliency in near-threshold processors, error-aware VLSI design for wide energy scalability, self-powered circuits. In 2009- 2011, he was Visiting Professor at BWRC ? University of California, Berkeley, investigating on next-generation ultra-low power circuits and wireless nodes. In the summer of 2007, he was a Visiting Professor at EPFL – Lausanne (Switzerland). He has authored or co-authored more than 180 publications on journals (70, mostly IEEE Transactions) and conference proceedings. One of them is the second most downloaded TCAS-I paper in 2013, and other two are among the most downloaded TVLSI papers in 2007. He is co-author of two books, Flip-Flop Design in Nanometer CMOS – from High Speed to Low Energy (Springer, 2013) and Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include ultra- ow power VLSI circuits, self-powered and wireless nodes, near-threshold circuits for green computing, error-aware and widely energy-scalable VLSI circuits, circuit techniques for emerging technologies. Prof. Alioto is an IEEE Senior Member, and was a member of the HiPEAC Network of Excellence (EU) and the MuSyC FCRP Center (US). In 2010-2012 he was the Chair of the ?VLSI Systems and Applications? Technical Committee of the IEEE Circuits and Systems Society, for which he was also Distinguished Lecturer in 2009-2010 and member of the DLP Coordinating Committee in 2011-2012. He currently serves as Associate Editor in Chief of the IEEE Transactions on VLSI Systems, and served as Guest Editor of various journal special issues (including the issue on ?Ultra-Low Voltage Circuits and Systems for Green Computing? published on Dec. 2012 on IEEE Transactions on Circuits and Systems ? part II). He also serves or has served as Associate Editor of a number of journals (IEEE Transactions on VLSI Systems, ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on CAS – part I, Microelectronics Journal, Integration ? The VLSI journal, Journal of Circuits, Systems, and Computers, Journal of Low Power Electronics, Journal of Low Power Electronics and Applications). He serves or has served as panelist for several funding agencies and programs (e.g., NSF, NanoTera, FP7). He was Technical Program Chair of the ICECS 2013, NEWCAS 2012 and ICM 2010 conferences, and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM).[/spoiler] |
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| 3:50 PM | Break | |||
| 4:00 PM | Connecting the Internet of Everything | Michael Stauffer | Qualcomm | |
| [spoiler title=”Abstract:“]This session focuses on IoE in the Smart or Connected Home. It first explores the connected home ecosystem centered around the home network and smart gateway, providing context for absorbing new IoE devices into this ecosystem. The talk then introduces the key Smart Home IoE connectivity technologies, beginning with a discussion of the key connectivity characteristics and tradeoffs among the technologies. Next the discussion summarizes and compares specific primary connectivity PHYs used to connect the various devices in the home and ? 802.11n, Bluetooth (BR/EDR & BLE), 802.15.4 (used for ZigBee), Z-Wave, and the new 802.11ah technology. The presentation will then describe 802.11ah in some detail since it is new on the scene and many may not be familiar with it. The discussion wraps up illustrating how the various PHYs match to specific applications and use cases. Biography: Mike Stauffer is a senior director of business development at Qualcomm. In this role, he is responsible for sourcing new business leads where Qualcomm Atheros? solutions can be applied to a variety of consumer electronics. Prior to this role, he managed carrier marketing and business development for Atheros Communications. Before his time at Qualcomm, Mike held a number of product marketing and business development roles at start-ups such as iBlast, Gain Micro Optics and Digital Video Systems. He holds both a Masters in Electrical Engineering from Stanford University and a Bachelor?s in Electrical Engineering from the Massachusetts Institute of Technology (MIT).[/spoiler] |
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| 4:50 PM | Standards for Constrained IoT Devices | Bill Curtis | ARM | |
| [spoiler title=”Abstract:“]Industry analysts foresee astonishingly rapid IoT business expansion between now and the end of the decade. Growth will be fueled by technical progress in two areas. First, new generations of IoT-optimized silicon platforms will reduce cost and power consumption while improving wireless network efficiency. Second, open industry standards are evolving to bring Internet-like scale to these new categories of IoT platforms. Standardization will enable independent development of solution components across the entire IoT value-chain, thereby increasing innovation while cutting costs. In this talk, we explore some of the key standards that will enable the INTERNET of Things to reach its full potential. Biography: Bill Curtis is Lead Strategist for the Internet of Things at ARM. Prior to this role, Bill was Senior Fellow and Design Engineer at AMD, CTO of Dell?s Consumer and Displays groups, and Director of Computer Sciences for Landmark Graphics / Halliburton. Bill is a systems architect with experience ranging from tiny embedded devices to high-performance computing environments. He is currently focused on integrating those two worlds.[/spoiler] |
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| 5:40 PM | Wrap up / Q&A | |||
| 5:45 PM | Wine & Cheese Reception | |||
| 6:45 PM | End of Reception | |||
Conference
| Mon 8/11 | Session | Title | Presenter | Affiliation |
| 8:15 AM | Breakfast | |||
| 9:15 AM | Welcome | Introductory Remarks | ||
| 9:30 AM | High Performance Computing | SX-ACE Processor: NEC’s Brand-New Vector Processor | Shintaro Momose | NEC |
| SPARC64 XIfx : Fujitsu’s next generation processor for HPC | Toshio Yoshida | Fujitsu | ||
| Anton 2: A 2nd-Generation ASIC for molecular Dynamics Simulation | J. Adam Butts and David E. Shaw | D.E. Shaw Research | ||
| 11:00 AM | Break |
| 11:30 AM | Keynote | Power Constraints: From Sensors to Servers | Mike Muller | ARM |
| 12:30 PM | Lunch | |||
| 1:30 PM | Mobile Processors | NVIDIA’s Tegra K1 System-on-Chip | Michael Ditty, John Montrym and Craig Wittenbrink | NVidia |
| Applying AMD’s “Kaveri” APU for Heterogeneous Computing | Dan Bouvier, Ben Sander | AMD | ||
| NVIDIA’s Denver Processor | Darrell Boggs, Gary Brown, Bill Rozas, Nathan Tuck and K S Venkatraman | Nvidia |
| 3:00 PM | Break | |||
| 3:30 PM | Technology | HBM: Memory Solution for Bandwidth-Hungry Processors | Joonyoung Kim and Kevin Tran | SK Hynix Inc |
| Improved 3D chip stacking with ThruChip wireless connections | Dave Ditzel, Tadahiro Kuroda and Stephen Lee | ThruChip Communications | ||
| CMOS Biochips for Point-of-Care Molecular Diagnostics | Arjang Hassibi | InSilixa |
| 5:00 PM | Break | |||
| 5:30 PM | ARM Servers | The AMD Opteron “Seattle”: A 64b ARM Dense Server Processor | Sean White | AMD |
| ARM Next-Generation IP Supporting LSI’s High-End Networking | Mike Filippo, Jamshed Jalal, Mark Werkheiser, Ann Chin, David Sonnier, Kent Fisher and Jeff Connell | ARM, LSI Logic | ||
| X-Gene2: 28nm scale-out processor | Gaurav Singh | Applied Micro |
| 7:00 PM | Reception |
| Tue 8/12 | Session | Title | Presenter | Affiliation |
| 7:00 AM | Breakfast | |||
| 8:00 AM | FPGAs | Design of a High-Density SOC-FPGA at 20nm | Brad Vest, Sean Atsatt and Mike Hutton | Altera |
| Large-Scale Reconfigurable Computing in a Microsoft Datacenter | Andrew Putnam, Adrian Caulfield, Eric Chung et al | Microsoft | ||
| Xilinx FPGAs case study: High capacity and Performance 20nm FPGAs | Steve Young, Dinesh Gaitonde and Trevor Bauer | Xilinx | ||
| SDA: Software-Defined Accelerator for Large-Scale DNN Systems | Jian Ouyang, Shiding Lin, Wei Qi, Yong Wang, Bo Yu and Song Jiang | Baidu |
| 10:00 AM | Break | |||
| 10:20 AM | High Performance ASICs | Hardware-Accelerated Text Analytics | Raphael Polig, Kubilay Atasu, Christoph Hagleitner et al | IBM |
| Myriad2 “Eye” of the Computational-Vision Storm | David Moloney, Brendan Barry, Richard Richmond et al | Movidius | ||
| Goldstrike 1: A 1st Generation Cryptocurrency Processor for Bitcoin Mining | Jim O’Connor, Timo Hanke, Javed Barkatullah and Ricky Lewelling | Cointerra | ||
| RayChip: Real-time Ray Tracing Chip for Embedded Applications | Woo-Chan Park, Hee-Jin Shin, Byoungok Lee et al | Siliconarts |
| 12:20 PM | Lunch | |||
| 1:20 PM | Keynote | The Internet of Everything: What is it? What’s driving it? What comes next? | Rob Chandhok | Qualcomm |
| [spoiler title=”Abstract:“] The Internet of Everything – where people, places, devices and machines are all interconnected and can easily interact – is emerging rapidly. It is generating enormous demand for data, redefining what gateways must do and requiring a host of new solutions, not the least of which is a common, open framework that enables devices, applications and services from any brand to easily connect and interact. This session will dive into the architectural implications of this transformation, the factors driving it and what is out over the horizon. Biography: Rob Chandhok is president of Qualcomm Interactive Platforms and senior vice president of Qualcomm Technologies, Inc. (QTI). He is responsible for Qualcomm strategies that address how people can take advantage of and benefit from the Internet of Everything, wearable computing and augmented reality as Qualcomm drives the next level of user experience in a massively interconnected and mobile-centric world. These responsibilities include the work he and his team do in helping to align QTI?s software and services initiatives ? and the innovation and development strategies upon which they are based ? for QTI?s mobile software technologies. Specific product offerings from Chandhok?s group ? which develops, tests and commercializes software and hardware products that provide users a ?digital 6th sense? ? include driving the horizontal ecosystem for the Internet of Everything via AllJoynTM, wearable computing via ToqTM and the vision-based computing that underlies Vuforia?sTM augmented reality experiences. Chandhok also leads Qualcomm Internet Services which is responsible for large-scale services, commercial deployments and VoIP solutions for mobile network operators. Previously, Chandhok spearheaded the strategic development for some of Qualcomm?s most significant projects. He was a key member of the management team that developed and launched the company?s Brew mobile software business, and he also led engineering and market development efforts for QChat, VoIP push-to-talk over CDMA IP data, a technology subsequently licensed by Sprint-Nextel. Also, as vice president of engineering and market development, he acted as the chief system architect for MediaFLO. Prior to that, Chandhok served as chief product officer of SunRocket. He established the company?s San Diego offices and brought his vision for IP-based home-centric data communications products and services to the company. Early in his career, Chandhok worked as a research computer scientist for more than 10 years at the Carnegie Mellon School of Computer Science. His work was published in the research areas of programming systems and computer-supported collaborative work. In 1993, Chandhok served as president of Within Technology, a company he founded to commercialize research and new product development in the area of computer-mediated communication. Chandhok holds 22 patents in software technologies and holds a Bachelor of Science degree in electrical engineering from Carnegie Mellon University.[/spoiler] |
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/tbody>
| 2:20 PM | Break | |||
| 2:40 PM | Dense Servers and Server Technology | SCORPIO: 36-Core Shared-Memory Processor with a Coherent Mesh | Chia-Hsin Owen Chen, Sunghyun Park, Suvinay Subramanian | MIT |
| Oracle’s Next Generation SPARC Cache Hierarchy | Ram Sivaramakrishnan, Sumti Jairath | Oracle | ||
| Unchaining the data center with Open Power: Reengineering a server ecosystem | Michael Gschwind | IBM | ||
| Intel C2000 Atom Microserver: Power Efficient Processing for the Data Center | Brad Burres, Johan Van de Groenendaal, Jonathan Robinson et al | Intel |
| 4:40 PM | Break | |||
| 5:00 PM | Big Iron Server | Performance Characteristics of the POWER8 Processor | Alex Mericas | IBM |
| Next Generation Oracle SPARC Processor | Stephen Phillips | Oracle | ||
| IvyBridge Server: Delivering Performance from Workstations to Mission Critical | Irma Esmer and Scott Murray | Intel |
[/tab]
[tab title=”Posters”]
Posters (** = Awarded Best Poster of Conference)
| Title | Presenter |
| Memory Processing Units ** | Jaikrishnan Menon, Lorenzo De Carli, VijayraghavanThiruvengadam Karthikeyan Sankaralingam and Cristian Estan* UW-Madison and *Google |
| Precision Refinement for Media-Processor SoCs: fp32! fp64 on Myriad | Tomasz Szydzik, University of Las Palmas of Gran Canaria, David Moloney, Movidius |
| Level-3 BLAS on Myriad Multi-Core Media-Processor | Tomasz Szydzik, University of Las Palmas of Gran Canaria, Marius Farcas, Valeriu Ohan, Codecart, David Moloney, Movidius |
| Bridge Chip Composing a PCIe Switch over Ethernet to Make a Seamless Disaggregated Computer in Data-Center Scale | Takashi Yoshikawa, Jun Suzuki, Green Platform Research Lab, Yoichi Hidaka, Junichi Higuchi, System Device Division, and Shinji Abe, IT Platform Division, NEC |
| Low Power Fixed-Latency DSP Accelerator with Autonomous Minimum Energy Tracking (AMET) | Chung-Hsun Huang1,3, Wei-Jen Chen1,3, Keng-Jui Chang1,3, Yi-Hsun Ting2,3, Keng-Chang Hsu1,3, Yu-Fu Pan1,3, Chao-Chun Chen1,3, Yuan-Hua Chu4, Tay-Jyi Lin2,3, and Jinn-Shyan Wang1,3 1Department of Electrical Engineering, National Chung Cheng University (CCU), Taiwan, 2Deptartment of Computer Science and Information Engineering, CCU, Taiwan, 3SoC/AIM-HI Centers, CCU, Taiwan 4Information and Communications Research Laboratories (ICL), Industrial Technology Research Institute (ITRI), Taiwan |
| A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode | Shiro Kamohara1, Nobuyuki Sugii1, Koichiro Ishibashi2, Kimiyoshi Usami3, Hideharu Amano4, Kazutoshi Kobayashi5, and Cong-Kha Pham2, 1Low-power Electronics Association & Project (LEAP), Tsukuba, Japan, 2The University of Electro-Communications, Tokyo, Japan, 3Shibaura Institute of Technology, Tokyo, Japan, 4Keio University, Yokohama, Japan, 5Kyoto Institute of Technology, Kyoto, Japan |
| Have Your Cake In Parallel And Eat It Sequen6ally Too! | Gagan Gupta, University of Wisconsin |
| High-level Synthesis of Memory Bound and Irregular Parallel Applications with Bambu | Vito Giovanni Castellana and Antonino Tumeo from Pacific Northwest National Laboratory, Richland, WA, USA; Fabrizio Ferrandi from Politecnico di Milano, DEIB – Milano, Italy |